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This chapter describes some minor changes that do not belong in any of the previous chapters about the kernel.
When reading the OS version identifier, R1 returns on exit the value:
A SWI has been added in RISC OS 3.5 to reset the computer. It is described overleaf.
Performs a hard reset
Does not exit!
Interrupt state is not defined
Fast interrupts are enabled
Processor is in SVC mode
This call performs a hard reset.
It is only available from RISC OS 3.5 onwards.