www.riscos.com Technical Support: Programmer's Reference Manual

Miscellaneous kernel items

Introduction and Overview

This chapter describes some minor changes that do not belong in any of the previous chapters about the kernel.

Changes to existing SWIs

OS_Byte 129

When reading the OS version identifier, R1 returns on exit the value:

• &A5 for RISC OS 3.5
• &A6 for RISC OS 3.6.

New SWI

A SWI has been added in RISC OS 3.5 to reset the computer. It is described overleaf.

SWI Calls

---

OS_Reset
(SWI &6A)

Performs a hard reset

On entry

--

On exit

Does not exit!

Interrupts

Interrupt state is not defined
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Irrelevant

Use

This call performs a hard reset.

It is only available from RISC OS 3.5 onwards.

Related SWIs

None

Related vectors

None